List of Takashi HIRAYAMA's Research Papers
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Our laboratory (Japanese)
Please feel free to ask me whenever you want to get reprints of my papers.
Here is my email address.
Journal Papers
- [AliHirYam2018] Ali, M.B., Hirayama, T., Yamanaka, K., and Nishitani, Y.,
``Function design for minimum multiple-control Toffoli circuits of reversible adder/subtractor blocks and arithmetic logic units,''
IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences
Vol. E101-A, No. 12, pp. 2231-2243, December 2018.
Official site:
IEICE.
Official PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of IEICE.
- [HirSugYam2014] Hirayama, T., Sugawara, H., Yamanaka, K., and Nishitani, Y.,
``A lower bound on the gate count of Toffoli-based reversible logic circuits,''
IEICE Trans. Information and Systems,
Vol. E97-D, No. 9, pp. 2253-2261, September 2014.
Official site:
IEICE.
Official PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of IEICE.
- [HigHirNis2009] Higashiohno, M., Hirayama, T., and Nishitani, Y.,
``A lower bound on the number of Toffoli gates in reversible logic circuits,''
IEICE Trans. A - Fundamentals of Electronics, Communications and Computer Sciences (Japanese Edition),
Vol. J92-A, No. 4, pp. 263-266, April 2009.
Official site:
IEICE.
Errata: Errata in the Japanese paper.
Draft PDF: Translation by the author. The above errata have been fixed in this PDF.
- [HirNis2009] Hirayama, T., and Nishitani, Y.,
``Exact minimization of AND-EXOR expressions of practical benchmark functions,''
Journal of Circuits, Systems, and Computers,
World Scientific Publishing Company,
vol.18, no.3, pp.465-486, May 2009.
Official site:
World Scientific.
Draft PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of JCSC.
- [IshHirKod04] Ishikawa, R., Hirayama, T., Koda, G., and Shimizu, K.,
``New three-level Boolean expression based on EXOR gates,''
IEICE Trans. Information and Systems,
vol.E87-D, no.5, pp.1214-1222, May 2004.
Official site:
IEICE.
Official PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of IEICE.
- [HirNisSat02d] Hirayama, T., Nishitani, Y., and Sato. T.,
``A faster algorithm of minimizing AND-EXOR expressions,''
IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences,
vol.E85-A, no.12, pp.2708-2714, Dec. 2002.
Official site:
IEICE.
Official PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of IEICE.
A sample program of "min-tau":
esop-multi-basic.tar.gz (ver. 2013-Jun-26):
This computes an exact minimum ESOP of a given logic function.
It supports multiple-output functions.
Another program that computes only tau (the term count of the minimum ESOP)
of a given function is also included.
This sample program is written in Common Lisp, and
different from the program used for the experiments in the above paper,
which was written in C language.
I am sorry, but the C version of "min-tau" will not be posted.
- [HirNagNis01] Hirayama, T., Nagasawa, K., Nishitani, Y., and Shimizu, K.,
``Double fixed-polarity Reed-Muller expressions:
a new class of AND-EXOR expressions for
compact and testable realization,''
Trans. IPS Japan, vol.42, no.4, pp.983-991, Apr. 2001.
Official site:
IPSJ.
Official PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of IPSJ.
- [HirNagShi01] Hirayama, T., Nagasawa, K., and Shimizu, K.,
``Fixed-polarity OR-AND-EXOR expressions and their minimization,''
Trans. IPS Japan, vol.42, no.4, pp.992--995, Apr. 2001.
Official site:
IPSJ.
Official PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of IPSJ.
- [HirKodNis99] Hirayama, T., Koda, G., Nishitani, Y., and Shimizu, K.,
``Easily testable realization based on
single-rail-input OR-AND-EXOR expressions,''
IEICE Trans. Information and Systems,
vol.E82-D, no.9, pp.1278-1286, Sep. 1999.
Official site:
IEICE.
Official PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of IEICE.
- [IshHirKod99] Ishikawa, R., Hirayama, T., Koda, G., and Shimizu, K.,
``EXOR decomposition with common variables
and its application to multiple-output networks,''
Journal of Circuits, Systems, and Computers,
World Scientific Publishing Company,
vol.9, nos.1&2, pp.83-97, 1999.
Official site:
World Scientific.
Draft PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of JCSC.
- [HirNisShi97] Hirayama, T., Nishitani, Y., and Shimizu, K.,
``Minimization of AND-EXOR expressions for symmetric functions,''
IEICE Trans. Fundamentals of Electronics,
Communications and Computer Sciences,
vol.E80-A, no.3, pp.246-249, Mar. 1997.
Official site:
IEICE.
Official PDF: The PDF of the paper is posted
as the author rights granted
under conditions of the copyright license of IEICE.
- [HirNis95a] Hirayama, T., and Nishitani, Y.,
``A simplification
algorithm of AND-EXOR expressions guaranteeing minimality for some
subclass of logic functions,''
IEICE Trans. Information and Systems D-I, vol.J78-D-I, no.4, pp.409-415, Apr. 1995. (in Japanese)
(Translation Paper:
``A simplification
algorithm of AND-EXOR expressions guaranteeing minimality for some
subclass of logic functions,''
System and Computer in Japan,
Vol.27, No.3, pp.18-25, 1996.)
Official site:
IEICE.
Draft PDF:
Translation by the author.
Conference Papers
- [HirTakNis2006] Hirayama, T., Takahashi, M., and Nishitani, Y.,
``Simplification of exclusive-or sum-of-products expressions through function transformation,''
Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems 2006, Singapore, pp.1482-1485, Dec. 2006.
Official site:
IEEE Xplore.
- [HirNis2006] Hirayama, T. and Nishitani, Y.,
``Efficient search methods for obtaining exact minimum AND-EXOR expressions,''
Proc. of 3rd IEEE International Workshop on Electronic Design, Test and Applications, Kuala Lumpur, Malaysia, pp.137-142, Jan. 2006.
Official site:
IEEE Computer Society Digital Library or
IEEE Xplore.
- [HirSatNis03] Hirayama, T., Sato, T., and Nishitani, Y.,
``Minimizing AND-EXOR expressions of some benchmark functions,''
Proc. of 6th International Symposium on Representations and Methodology of Future Computing Technologies, Trier, Germany,
pp.69-76, Mar. 2003.
Official site:
RM2003.
- [HirNisSat02c] Hirayama, T., Nishitani, Y., and Sato, T.,
``A faster algorithm of minimizing AND-EXOR expressions,''
Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems 2002,
Bali, Indonesia, vol.2, pp.293-298, Oct. 2002.
(Preliminary work of [HirNisSat02d])
Official site:
IEEE Xplore.
- [IshIgaHir02c] Ishikawa, R., Igarashi, T., Hirayama, T., and Shimizu, K.,
``Pseudocube-based expressions to enhance testability,''
Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems 2002,
Bali, Indonesia, vol.2, pp.305-310, Oct. 2002.
Official site:
IEEE Xplore.
- [IshHirKod00b] Ishikawa, R., Hirayama, T., Koda, G., and Shimizu, K.,
``Factorization to enhance random pattern testability of EXOR based circuits,''
Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems 2000,
Tianjin, China, pp.795-798, Dec. 2000.
Official site:
IEEE Xplore.
- [HirKodNis98a] Hirayama, T., Koda, G., Nishitani, Y., and Shimizu, K.,
``Easily testable realization based on OR-AND-EXOR expansion
with single rail inputs,''
Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems '98,
Changmai, Thailand, pp.371-374, Nov. 1998.
(Preliminary work of [HirKodNis99])
Official site:
IEEE Xplore.
- [HirIshKod98b] Hirayama, T., Ishikawa, R., Koda, G., and Shimizu, K.,
``EXOR decomposition with fixed variables
and its application to multiple-output networks,''
Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems '98,
Changmai, Thailand, pp.375-378, Nov. 1998.
(Preliminary work of [IshHirKod99])
Official site:
IEEE Xplore.
- [HirNis95b] Hirayama, T., and Nishitani, Y.,
``A simplification algorithm of AND-EXOR expressions for multiple-output
functions,''
Proc. of IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in
Circuit Design '95, Tokyo, Japan, pp.88-93, Aug. 1995.
Official site:
RM1995.